This invention relates to integrated circuits and more particularly, to integrated circuits with electrostatic discharge protection circuitry.
Integrated circuits are often exposed to potentially damaging electrostatic charge. For example, a wafer of integrated circuit dies may be exposed to electric charge during integrated circuit fabrication. Such charge may arise from the use of plasma etching techniques or other processes that produce charged particles. As another example, an integrated circuit package may be exposed to electrostatic charge when a worker inadvertently touches exposed pins on the integrated circuit package or when the integrated circuit package becomes electrostatically charged due to movement of the package in a tray. Electrostatic charge generated in this way can oftentimes damage sensitive circuitry on an integrated circuit (i.e., transistors and other electrical devices on the integrated circuit can be damaged when exposed to excessive current).
To reduce the impact of electrostatic charge on sensitive circuitry, integrated circuits may be provided with electrostatic discharge (ESD) protection circuitry. Electrostatic discharge protection circuitry is typically coupled to input-output pins on an integrated circuit. As integrated circuit devices scale towards more advanced technology nodes (i.e., 28 nanometers and beyond), ESD requirements may be increased in order to protect smaller transistors from being damaged during fabrication and other device packaging/assembly operations.
One way of satisfying the increasing ESD requirements is to increase the size of the ESD protection circuitry so that more ESD current can be absorbed with the ESD protection circuitry. Upsizing the ESD protection circuitry, however, increases the amount of capacitance at the input-output pins. Increasing capacitive loading at the input-output pins may undesirably limit the high-speed communications performance of an integrated circuit.